(STL.News) – Astera Labs Inc., in collaboration with Synopsys, Inc. (Nasdaq: SNPS), and Intel (Nasdaq: INTC), today announced an industry-first demonstration of a complete PCI Express® (PCIe®) 5.0 system, delivering 32 GT/s speeds for next-generation server workloads. The end-to-end solution showcases system-level multi-vendor interoperability between Intel’s PCIe 5.0 test chip, Synopsys’ silicon-proven DesignWare® Controller and PHY IP for PCIe 5.0, and Astera Labs’ industry-first Smart Retimer SoC for PCIe 5.0. The companies will demonstrate the solution at the PCI-SIG Developers Conference in Taipei, October 28-29.
“We’re excited to collaborate with Synopsys and Intel to prove to the industry that we are ready for PCIe 5.0 customers and we are actively sampling our retimer SoC now,” said Jitendra Mohan, chief executive officer, Astera Labs. “We’ve delivered the world’s first PCIe 5.0 Smart Retimer that provides backwards compatibility, enabling developers to future-proof their systems by leveraging the solution for PCIe 4.0 now and having a pin-compatible solution for PCIe 5.0 when systems are available in 2020. Collaborating with Synopsys and Intel helped accelerate our development process.”
“Synopsys, Astera Labs, and Intel are collaborating to help the PCI Express ecosystem to meet their advanced requirements for networking, storage, and machine learning applications that require extremely high-speed interfaces,” said John Koeter, vice president of marketing for IP at Synopsys. “By providing a complete IP solution for PCI Express 5.0, Synopsys enables companies like Astera Labs to get an early start on their designs and benefit from Synopsys’ proven expertise in PCI Express to achieve first-pass silicon success for their SoCs.”
“PCIe 5.0 technology adoption is crucial as the industry adds accelerated, heterogenous computing architectures and workload-optimized platforms to support the next generation of data-centric platform,” said Jim Pappas, director of Technology Initiatives at Intel. “Intel is a staunch proponent of PCIe 5.0 architecture and we are racing to deliver robust solutions that deliver faster speeds and lower latency to meet data centric workload requirements. We are pleased to collaborate with Astera Labs and Synopsys on pioneering this new ecosystem.”
Demonstration at PCI-SIG Developers Conference in Taipei
The joint PCIe 5.0 demonstration will be showcased in the Synopsys Booth at PCI-SIG DevCon Taipei, October 28-29 at the Taipei Marriott Hotel.